1. Field of the Invention
This invention relates to computer systems, and more particularly, the handling of interrupts by a processor of a computer system.
2. Description of the Related Art
Computer systems typically include a number of devices that perform various functions. A typical computer system includes at least one processor and may have a number of peripheral devices coupled to one or more buses. The one or more buses may be directly coupled to the processor, or may be coupled to the processor through a bus bridge. Examples of peripheral buses include the peripheral component interface (PCI) bus and the universal serial bus (USB). In addition to peripheral devices coupled to the peripheral buses, a computer system may also include various input/output devices (e.g., keyboard, mouse) as well as storage devices (e.g., a hard disk drive). These devices in a computer system may signal a need to communicate with the processor by using an interrupt.
An interrupt signal (often times referred to as an interrupt request) may be conveyed to the processor through an interrupt line. After receiving the interrupt request, the processor may temporarily halt the execution of an instruction stream to deal with the, interrupt by performing a service routine, which may resolve the condition that initially triggered the interrupt request.
As the functionality and complexity of computer systems has increased, the number of sources for interrupts has also increased. Often times, interrupts are arranged into groups. Different service routines may be performed for each interrupt of an interrupt group. A given processor may also have the capability of enabling or disabling specific interrupts, and may also include priority encoding logic to determine which interrupt should be resolved first when more than one interrupt request is pending.
When an interrupt request is received, a processor may be required to perform a number of steps before the request can be resolved. When a large number of interrupts are present and arranged into groups, the processor may first execute instructions to determine which one of the interrupts of the group to which the interrupt request corresponds (i.e. the source of the interrupt). Following this determination, additional instructions may be executed in order to determine if the interrupt corresponding with the interrupt request is enabled or not. If the corresponding interrupt is enabled, the processor may be required to perform an additional step of determining the source of the interrupt and whether or not it is enabled, the processor may be required to resolve the priority of the interrupt with respect to a number of pending interrupt requests. Due to these various factors, it may take a significant amount of time for a processor to resolve each interrupt request. The amount of time required to resolve each interrupt request can have an adverse affect on system performance. Furthermore, the amount of time required to resolve interrupt requests may exceed operating margins for some devices which may generate interrupts, thus preventing their use in the system.